Load compensation technique for reactive impedance transformation amplifier output stage

ABSTRACT

A method of selectively reducing the impedance presented to the load of a reactive impedance transformation amplifier output stage reduces distortion caused by load reactance. A control circuit is interconnected to a gated switch on at least one side of the load, and the switch is controlled to shunt back-EMF from the load. In one embodiment, the shunting action is initiated when the released energy would approach zero with a purely resistive load. Since the delay time may be a function of energy released, the delay from energy release to shunt initiation is optimally a function of the energy storage time of the inductor. In the event that this energy storage time is regulated using feedback, the shunt delay should be as well regulated, to accentuate the regulatory action. In a more comprehensive embodiment, the amplifier output polarity is inverted and its output caused to be a function of the positive error in the circumstance of a substantial positive error, such as that caused by an inductive load.

This application is a 371 of PCT of PCT/US00/13852 filed May 19, 2000which claims benefit of 60/134,817 filed May 19, 1999 and claims benefitof 60/174,381 filed Jan. 5, 2000.

FIELD OF THE INVENTION

This invention relates generally to switching amplifiers and, inparticular, to apparatus and methods for compensating the output stagein amplifiers of this type so as to reduce back-EMF.

BACKGROUND OF THE INVENTION

Amplifiers with reactive impedance transformation output stages, asshown in U.S. Pat. No. 5,610,553 entitled “Switching Amplifier withImpedance Transformation Output Stage,” provide high efficiency at highvoltage or current levels. The teachings of this patent are incorporatedherein by reference.

Unlike conventional amplifiers, however, impedance transformationswitching amplifiers do not exhibit symmetrical or constant drivecapability. As a result, unless compensated, back-EMF from the load canseriously distort the output waveform. As well, inductance inanti-aliasing output filters commonly used with such switchingamplifiers can seriously degrade performance.

A need accordingly exists for a compensation method to counteractasymmetrical and variant output impedance in switching amplifiers ofthis type.

SUMMARY OF THE INVENTION

This invention provides circuitry for reducing and, preferablyeliminating, load-induced back-EMF in impedance-transformation switchingamplifiers. Different embodiments are deployed, depending upon theseverity of the error. Broadly a gated switch coupled to the load isdriven by a control circuit appropriately timed to shunt back-EMF. Inthe event that the amplifier is already equipped with gated switchesused to transfer energy representative of an input signal to and fromthe load impedance, at least some of the same gated switches mayconveniently be used for back-EMF control. In preferred configurations,separate gated switches are used on both sides of the load, and thecontrol circuit is configured to drive all of the switches.

If the error is relatively minor, the control circuit may include atimer operative to activate the gated switch after a fixed timeinterval. Alternatively, the time interval may be varied in relation tothe time associated with energy dissipation through a purely resistiveload. If the energy storage time of the load is regulated usingfeedback, the initiation of the shunting action is also preferablyfeedback-regulated.

If the error is more severe, an error detection circuit is used todetermine if the amplifier output voltage exceeds a level representativeof a desired input, and circuitry is added for inverting the polarity ofthe output if the level is exceeded. In accordance with this alternativemethod, the amplifier output polarity is inverted and its output causedto be a function of the positive error in the circumstance of asubstantial positive error, such as that caused by an inductive load.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a reactive impedance transformationamplifier output stage incorporating an embodiment of the invention forcompensating a relatively minor error;

FIG. 2 shows the control and output voltage waveforms of the circuit inFIG. 1, with the invention disabled, thus yielding waveforms typicallyseen in reactive impedance transformation amplifiers;

FIG. 3 shows the control and output voltage waveforms of the circuit inFIG. 1, with the invention being enabled; and

FIG. 4 is a schematic diagram of the invention compensating a relativelymajor error.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic diagram of an output stage incorporating anembodiment of the invention used to correct relatively minor errors.Switch 125 is included to show operation with and without thefunctionality of the invention.

Incoming data 100 is supplied to full-wave rectifier 118 and comparator119. The absolute value of incoming data 100 is thus supplied to pulsewidth modulator 121, while its sign is supplied by comparator 119 toswitching device 101 and OR gate 124, which drives switching device 104as voltage 110. The complement of the sign is provided by inverter 120to switching device 109 and OR gate 123, which drives switching device102 as voltage 108. The polarity if the incoming data 100 thus controlswhich pair of switching devices 101 and 104, or 103 and 102, isactivated.

The output of pulse-width modulator 121 is supplied as voltage 106 toswitching device 105, which stores energy in inductor 111 whenactivated. When switching device 105 is released, stored energy isstored in capacitor 113 and released ultimately into load 117 throughdiode 112 and either switching device 101 and inductor 114, or switchingdevice 103 and inductor 115, depending on polarity of incoming data 100.Current return for load 117 is provided by either inductor 115 andswitching device 104, or inductor 114 and switching device 102, againdepending on polarity of incoming data 100. Capacitor 116, inconjunction with inductors 114 and 115, serves to filter the voltageapplied to load 117.

With switch 125 in the ‘B’ position, operation is typical of this classof amplifier. Energy is stored in inductor 111 when charged by switchingdevice 105 under control of voltage 106 from pulse-width modulator 121.When switching device 105 is turned off, the stored energy is releasedthrough diode 112, limited by capacitor 113, and applied to load 117through either switching device 101 or switching device 103, undercontrol of voltage 107 or voltage 109, respectively, the assertions ofwhich are mutually exclusive. In this manner, the desired outputpolarity at load 117 is effected.

Inductors 114 and 115, and capacitor 116 serve to remove switchingcomponents from the energy supplied to load 117. The return path for thestored energy released from inductor 111 is provided by either switchingdevice 102 or switching device 104, under control of voltage 108 andvoltage 110, respectively, the assertions of which are again mutuallyexclusive.

The voltage waveforms of FIG. 2 show operation of the circuit of FIG. 1when switch 125 is in the ‘B’ position, disabling functionality of thepresent invention It will be seen that further input to switchingdevices 102 and 104 by OR gates 123 and 124, respectively, is obviated,and operation is that typical of a reactive impedance transformationamplifier. Control voltages 201, 202, 203, 204, and 205 of FIG. 2correspond to control voltages 106, 107, 108, 109, and 110,respectively, of FIG. 1. Voltage 206 shows activity at the junction ofswitching devices 101 and 102 of FIG. 1. It can be seen that, under thecondition of diminishing output shown at point 207, the decay slope ofvoltage 206 is considerably less steep than the previous decay slopes atincreasing or constant output. This voltage rise is due to back EMF fromthe load attempting to maintain the previous electrical and mechanicalspeaker conditions, and represents a considerable distortion.

When switch 125 is in the ‘A’ position, OR gates 123 and 124 allowassertion of switching devices 102 and 104, respectively, by the outputof monostable timer 122. At the falling edge of voltage 106 (release ofswitching device 105), monostable timer 122 deasserts its output 126 foreither a fixed time interval, or a time interval that is a function ofthe absolute value of the incoming data (shown by dotted data path). Atexpiration of this time interval, monostable timer 122 asserts itsoutput, which, when enabled by switch 125, is applied to OR gates 123and 124. OR gates 123 and 124 pass this assertion to switching devices102 and 104, respectively.

Note that either switching device 102 or 104 is activated at any giventime by the action of comparator 119 and inverter 120, under control ofthe polarity of incoming data 100, as mentioned previously. At the pointof output assertion of monostable timer 122, therefore, both switchingdevices 102 and 104 are activated, effectively shunting any voltageextant across load 117, through inductors 114 and 115. The timinginterval of monostable timer 122 is optimally adjusted to approximatethe time necessary for energy depletion in capacitor 113.

Voltage waveforms of FIG. 3 show operation of the circuit of FIG. 1 whenswitch 125 is in the ‘A’ position, enabling functionality of the presentinvention Referring now to FIG. 3, control voltages 301, 302, 303, 304,and 305 correspond to control voltages 106, 107, 108, 109, and 110,respectively, of FIG. 1. Voltage 306 shows activity at the junction ofswitching devices 101 and 102 of FIG. 1. An important difference betweenthe control voltages 301, 302, 303, 304, and 305 of FIG. 3 and controlvoltages 201, 202, 203, 204, and 205 of FIG. 2 is the assertion ofvoltage 303 at a point after release of voltage 301 until the nextrelease of voltage 301. In correlating this voltage to the schematic ofFIG. 1, it can be seen that the net effect is one of selectivelyshunting any voltage present at the junction of switching devices 101and 102 of FIG. 1. Back EMF injected by load 117 is thereby shunted.Although a single polarity is shown, it is assumed that a correlativeaction is as well asserted at control voltage 110 of FIG. 1.

The ideal time at which to initiate the shunting action described hereinis the time at which the released energy from capacitor 113 of FIG. 1would approach zero with a purely resistive load. In that this delaytime can be a function of energy released, the delay from energy releaseto shunt initiation is optimally a function of the energy storage timeof the inductor. In the event that this energy storage time is regulatedusing feedback the shunt delay should be as well regulated to accentuatethe regulatory action.

FIG. 4 is a schematic diagram of a preferred circuit according to theinvention for correcting relatively large errors. Incoming signal 400feeds both full-wave rectifier 401 and comparator 402, which indicatesdesired output polarity at its output. The output of comparator 402drives one input of exclusive-OR gate 408 which, in turn, either turnson switching devices 415 and 418 through inverter 412 (when high), oractivates switching devices 412 and 419 through inverter 412 when low.

The output of full-wave rectifier 401 drives both the ‘0’ input ofmultiplexer 405 and the inverting input of error amplifier 403, thenon-inverting input of which is driven by the common cathodes of diodes420 and 421. The anodes of diodes 420 and 421 are individually connectedeach to one terminal of the load 415, thus yielding the absolutepositive output voltage of the amplifier at their common cathodes. Thuserror amplifier 403 outputs a positive voltage if the amplifier outputvoltage exceeds that indicated by the desired input, and a negativevoltage if the amplifier output voltage is less than that indicated bythe desired input.

The output of error amplifier 403 drives both the non-inverting input ofcomparator 404 and the ‘I’ input of multiplexer 405. Comparator 404compares the output of error amplifier 403 with a reference, outputtinga logical one when the amplifier output at the load exceeds thatindicated by the desired input by a margin indicated by the referencevoltage at its inverting input.

The output of comparator 404 drives the control input of multiplexer 405and the second input of exclusive-OR gate 408. Thus, when the output ofcomparator 404 is a logical zero, multiplexer 405 supplies the desiredinput to pulse-width converter 406, and the indicated input polarity toswitching devices 412, 413, 418, and 419. However, when the output ofcomparator 404 is a logical one, multiplexer 405 now supplies the outputof error amplifier 403 (positive error) to pulse-width converter 406,and the indicated input polarity to switching devices 412, 413, 418, and419 is inverted by exclusive-OR gate 408. Pulse-width converter 406 isperiodically triggered by clock source 407.

The output of pulse-width converter 406 drives switching device 409,which stores charge in inductor 410. At release, this charge passesthrough diode 411 and is presented to one terminal of load 415 througheither switching device 412 and inductor 414, or switching device 418and inductor 416, depending on the current output of exclusive-OR gate408 noted earlier. In either event, the voltage presented to the load isfiltered by capacitor 417.

By this method, the amplifier output polarity is inverted and its outputcaused to be a function of the positive error in the circumstance of asubstantial positive error, such as that caused by an inductive load.

I claim:
 1. Distortion-control apparatus for use with a supply voltage,comprising: a switching amplifier output stage of the type whichperforms a variable-impedance transformation on a pulsewidth-modulatedinput signal and couples the output to a reactive load, includingcircuitry enabling the output to operate at voltage in excess of supplyvoltage; a gated switch coupled to the load impedance; and a controlcircuit driving the gated switch so as to shunt back-EMF (electromotiveforce).
 2. The circuitry of claim 1, including a gated switch coupled toeach side of the load, and wherein the control circuit drives bothswitches.
 3. The circuitry of claim 2, wherein a plurality of gatedswitches are to transfer energy representative of an input signal to andfrom the load impedance, and wherein at least some of the same gatedswitches are driven by the control circuit.
 4. The circuitry of claim 1,wherein the control circuit is a timer operative to activate the gatedswitch after a fixed time interval.
 5. The circuitry of claim 4, whereinthe time interval is related to the time associated with energydissipation through a purely resistive load.
 6. The circuitry of claim1, wherein: the output coupled to the load is regulated using feedback;and the initiation of the shunt is also feedback-regulated.
 7. Thecircuitry of claim 1, wherein: the amplifier is fed by incoming data;and the control circuit is operative to activate the gated switch as afunction of the absolute value of the incoming data.
 8. The circuitry ofclaim 1, wherein the control circuit further includes: an errordetection circuit for determining if the amplifier output voltageexceeds a level representative of a desired input; and circuitry forinverting the polarity of the output If the level is exceeded.
 9. Thecircuitry of claim 8, wherein: the amplifier includes a pulse-widthconverter for converting incoming data into a pulse-width modulatedsignal coupled to the load through a plurality of gated switches; andthe circuitry for inverting the polarity of the output further includesa multiplexer for supplying the output of error detection circuit to thepulse-width converter.
 10. The circuitry of claim 9, wherein at leastsome of the gated switches used to couple the pulse-width modulatedsignal to the load arc also driven by the control circuit.
 11. Thecircuitry of claim 1, wherein the input signal to the amplifier isanalog or digital.
 12. The circuitry of claim 1, wherein the gatedswitch is a field-effect transistor.
 13. Distortion control apparatusfor use with a supply voltage, comprising: a switching amplifier outputstage of the type which performs a variable-impedance transformation ona pulsewidth-modulated input signal and couples the output to a reactiveload; including circuitry enabling the output to operate at voltage inexcess of supply voltage; a controlled switch in an electrical path withthe load impedance; and circuitry operative to control the switch so asto shunt back-EMF (electromotive force) injected by the load.
 14. Theswitching amplifier output stage of claim 13, wherein: the output iscoupled bidirectionally to the load impedance; and the circuitry isoperative to control switches on both side of the load.
 15. Theswitching amplifier output stage of claim 13, wherein: a plurality ofelectrically controlled switches are used to couple thepulsewidth-modulated input signal to the load impedance; and at leastone of the switches is controlled by the circuitry to shunt back-EMF(electromotive force) injected by the load.